Mismatch in tap delay lines (TDLs), among other things, can limit the resolution of digital frequency synthesizers and digital phase modulators. (Such devices may be used in amplifiers and transmitter circuits such as those described in U.S. Pat. No. 7,715,493, filed on Aug. 14, 2006, incorporated by reference herein.) If the mismatch between elements is not addressed, noise folding and spurs can degrade performance characteristics such as signal to noise ratio (SNR) and other performance characteristics. Accordingly, new circuits and methods for addressing delay stage errors may be desired.